The trend in the electronics industry is to achieve ever faster switching speeds and increased circuit densities at the component and system levels. Another trend has been to reduce operating voltages and power consumption. These trends are placing more stringent demands on the on-die power distribution systems of integrated circuits, such as microprocessors. For example, higher switching speeds and clock frequencies lead to increased current demands and to higher inductive noise (L di/dt) on the power grid. Power saving modes of operation lead to large and rapid swings in current demand from the power distribution system. The lowering of operating voltages concomitantly narrows the voltage regulation window of the on-die supply voltage level (for example maintaining the supply voltage within 10% peak-to-peak). Increased power noise (from switching currents and power saving modes) and narrowing of the voltage regulation window (from reduced operating voltages) have pushed designers to explore on-die voltage regulation and power distribution techniques to achieve successful chip level and system level designs.